Field effect transistor circuit arrangement

ABSTRACT

In a circuit arrangement having a plurality of field effect transistors which are connected in series and operate simultaneously, the circuit arrangement is free from restriction of an operating frequency and it is not necessary to provide an individual power source for gate biasing, so that the construction of the circuit arrangement is simplified and the cost is reduced. 
     A gate drive pulse is applied to the gate of the field effect transistor (Q2) on a common potential point side. A parallel connection circuit having a first resistor (R3) and a first capacitor (C3) is coupled between the gate of the other field effect transistor (Q1) and the common potential point side. A parallel connection circuit having a second resistor (R4) and a second capacitor (C4) is coupled between the first electrode (e.g. drain) and the gate of the other field effect transistor. A capacitance of the first capacitor is larger than that of the second capacitor, so that the other field effect transistor is sufficiently shifted to a conductive state when the gate drive pulse is applied to the field effect transistor on the common potential side.

DESCRIPTION

1. TECHNICAL FIELD

The present invention relates to a field effect transistor circuitarrangement having a plurality of insulated gate field effecttransistors such as MOS type field effect transistors (referred to asMOS FET hereinafter) connected in series to be operable under a highvoltage condition.

2. BACKGROUND ART

The voltage withstand between the drain and source of a MOSFET currentlycommercially available is substantially 400 V at most. Accordingly, inorder to operate the MOSFET at 300 V or more for practical use, it isnecessary to connect a plurality of MOSFETs in series to increase thevoltage withstand. To this end, circuit arrangements as shown in FIGS. 1and 2 have hitherto been used.

In a circuit arrangement shown in FIG. 1, a pulse transformer isemployed to provide two or more gate drive signals which are isolatedfrom each other. That is, in FIG. 1, a gate drive signal Vin is appliedto a primary winding W1 of a pulse transformer PT. Individual outputpulses obtained from secondary windings W2 and W3 are appliedrespectively to the gates of n-channel MOSFETs Q1 and Q2 connected inseries. ZD1 and ZD2 are protective Zener diodes each for restricting thegate input signal so that a voltage between the gate and source does notexceed a breakdown voltage between the gate and source. The drain of theMOSFET Q1 is connected to a power source Vs via a load resistor RL andthe source of the MOSFET Q1 is connected to the drain of the MOSFET Q2,the source of which is connected to a common potential point. This drivemethod which uses the pulse transformer has frequently been used for theseries operation of bipolar transistors and thyristers, or the like. Inthe drive method, however, the operating frequency range of the gatedrive signal Vin is limited by characteristics of the pulse transformerused and in particular the limited frequency range causes a problem whenthe operating frequency is low, ranging in the order to several KHz to100 KHz so that the conduction period of time is long.

A circuit arrangement of FIG. 2 illustrates a drive method of the typein which a pulsive drive signal is applied to one of two elements forseries operation and a DC voltage is applied to the other element. InFIG. 2, like reference numerals are used to designate like portionsshown in FIG. 1. In the conventional drive method shown in FIG. 2, thegate drive signal Vin is directly applied to the gate of the MOSFET Q2and a DC voltage Vdc is applied to the gate of another MOSFET Q1,through a parallel circuit consisting of a resistor R1 and a capacitorC1. A parallel circuit consisting of a resistor R2 and a capacitor C2 isconnected between the gate and drain of the MOSFET Q1. Further, theresistors R1 and R2 form a voltage divider for determining an actualbias voltage applied to the gate of the MOSFET Q1. The capacitors C1 andC2 are used for correcting transient voltage share across the MOSFET Q1at the time of the switching. The respective circuit constants of thoseresistors and capacitors have been selected to be C1/C2≈R2/R1 and thecapacitance values of the capacitors C1 and C2 have been extremelysmall, for example, several tens pF. According to this drive method, theoperating frequency range is not limited, unlike the method shown inFIG. 1. If, however, the power source voltage (e.g. 400 V) of the MOSFETis taken into consideration, it is necessary to provide a power source(e.g. 10 V) for the gate drive independently or to apply a given voltagefrom the power source of MOSFET to the gate of the MOSFET through avoltage dividing circuit having a large power consumption. In thisrespect, the drive method has problems in terms of cost and convenience.

DISCLOSURE OF INVENTION

Accordingly, an object of the present invention is to provide a fieldeffect transistor circuit arrangement which, in driving field effecttransistors connected in series, eleminates the defects of theabove-described conventional drive methods without the restriction ofthe operating frequency and the provision of a separate DC power source.

According to this invention, in order to achieve the above object, thereis provided a field effect transistor circuit arrangement including aplurality of field effect transistors, each having a first electrode(drain electrode) and a second electrode (source electrode) and acontrol electrode, which are connected in series between a power sourcevoltage point and a common potential point, in which a control pulse isapplied to the control electrode (gate electrode) of the field effecttransistor on the side of the common potential point, a first parallelconnection circuit having a first resistor and a first capacitor iscoupled between the control electrode of each of the remaining fieldeffect transistors and the common potential point, and a second parallelconnection circuit having a second resistor and a second capacitor iscoupled between the first parallel connection circuit and the firstelectrode of the corresponding field effect transistor, whereby theremaining field effect transistors are changed to a sufficientlyconductive state at the time that the control pulse is applied to thefield effect transistor on the side of the common potential point.

In a preferred embodiment of the present invention, a Zener diode isconnected between the second electrode and the control electrode of eachof the field effect transistors for the protection thereof so that avoltage applied between the control electrode and the second electrodeof each of the corresponding field effect transistors does not exceed abreakdown voltage between the control electrode and the secondelectrode.

Another preferred embodiment of the invention has a third resistor forcurrent restriction which is connected between the control electrode ofeach of the remaining field effect transistors and a connection pointbetween the first and second parallel connection circuits.

Yet another preferred embodiment of the invention has fourth resistorseach inserted between the first electrode and the second electrode ofeach of the field effect transistors, for correcting an unbalance ofvoltages shared by the respective field effect transistors due tovariations of the characteristics of leak current between the first andsecond electrodes among the field effect transistors.

In still another embodiment of the invention, a series connectioncircuit having a fifth resistor and a third capacitor is connectedbetween the first electrode and the second electrode of each of thefield effect transistors, for correcting an unbalance of voltages sharedby the corresponding field effect transistors due to variations ofswitching characteristics among the field effect transistors.

In the present invention, it is preferable to select a capacitance ofthe first capacitor to be larger than that of the second capacitor. Thecapacitance of the first capacitor is approximately 5 to 10 times of astatic input capacitance of the corresponding field effect transistor.Furthermore, a capacitance of the second capacitor is selected to bewithin a range of about 2/3 to 1/several of the capacitance of the firstcapacitor.

According to one aspect of the present invention, there is provided afield effect transistor circuit arrangement including a plurality offield effect transistors having first and second electrodes and acontrol electrode, and a load which are connected in series between apower source voltage point and a common potential point, in which acontrol pulse is applied to the control electrode of the field effecttransistor on the side of the common potential point, a parallelconnection circuit having a resistor and a capacitor is connectedbetween the common potential point and the control electrode of thefield effect transistor adjacent to the field effect transistor on theside of the common potential point among the remaining field effecttransistors, a plurality of circuits having resistors and capacitorsconnected in parallel are connected in series between the parallelconnection circuit and the first electrode of the field effecttransistor on the side of the power source voltage and respectiveconnection points of these series connected circuits are connectedsequentially and correspondingly to the respective control electrodes ofthe remaining field effect transistors, whereby the remaining fieldeffect transistors are changed to a sufficiently conductive state at thetime that the control pulse is applied to the field effect transistor onthe side of the common potential point.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1 and 2 are circuit diagrams showing two embodiments of aconventional series connection type field effect transistor drivecircuit;

FIG. 3 is a circuit diagram showing an embodiment of a circuitarrangement of a field effect transistor drive circuit according to thepresent invention;

FIG. 4 is a signal waveform diagram illustrating examples of waveformsof voltages and currents at the respective portions of the circuitarrangement shown in FIG. 3;

FIG. 5 is a signal waveform diagram illustrating waveforms of a currentand a voltage depicted when a MOSTFET is turned on; and

FIGS. 6 and 7 are circuit diagrams showing other embodiments of thepresent invention.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in detail referring to theaccompanying drawings.

A circuit arrangement using two MOSFETs connected in series isillustrated in FIG. 3, as an embodiment of a field effect transistorcircuit arrangement according to the present invention. In FIG. 3, likereference symbols are used for designating corresponding portions shownin FIG. 2. In the embodiment shown in FIG. 3, while the supply of a gatedrive signal Vin to the gate (a node E) of a MOSFET Q2 is performed in asimilar manner as that of the drive method shown in FIG. 2, a gate biascircuit for a MOSFET Q1 has the following construction. Between the gate(a node D) of a MOSFET Q1 and a common potential point is connected inseries a current limiting resistor RG and a parallel circuit having aresistor R3 and a capacitor C3. Between a node G between the resistor RGand the parallel circuit R3, C3 and the drain of the MOSFET Q1 isconnected a parallel circuit having a resistor R4 and a capacitor C4.The circuit having the resistors R3 and R4, and the capacitors C3 and C4forms a gate bias circuit for providing a proper positive gate pulse tothe gate of the MOSFET Q1 over a desired period of time. Note here thatthe gate bias circuit does not require the power supply thereto from anadditionally provided DC power source, unlike the conventional circuitarrangement, and is connected merely between the power source Vs and thecommon potential point. The resistance values of the resistors R3 and R4are selected to be such a high resistance as to provide sufficientvoltage division for the leak current to the MOSFET Q1 and a Zener diodeZD1. In FIG. 3, between the drain (node A) and the source (node B) ofthe MOSFET Q1 is connected a parallel circuit having a resistor RE and aserial circuit having a resistor RS and a capacitor CS. Similarly,between the drain (node B) and the source (node C) of the MOSFET Q2 isconnected a parallel circuit having a resistor RE and a serial circuithaving the resistor RS and the capacitor CS. The resistors RE are usedfor correcting an unbalance of voltages shared by the MOSFETs Q1 and Q2due to a difference between the leak current characteristics between thedrains and the sources of the respective MOSFETs Q1 and Q2. The seriescircuits RS, CS are for correcting an unbalance of voltages shared bythe MOSFETs Q1 and Q2 due to a difference between the switchingcharacteristics of the MOSFETs Q1 and Q2.

In the circuit shown in FIG. 3, if the respective values of theresistors R3 and R4, and the capacitors C3 and C4 are determined in thesame design manner as the respective values of the resistors R1 and R2,and the capacitors C1 and C2 in FIG. 2, the voltage V_(DB) between thegate and the source of the MOSFET Q1 is lowered to several volts orless. Such a low voltage may insufficiently turn on the MOSFET Q1. Inview of this problem, the resistances and the capacitances of thoseresistors and capacitors, particularly the capacitors C3 and C4 aredetermined in the following manner according to the invention.

The manner of determining those values in accordance with the inventionwill be explained while the operation of the circuit arrangement of thepresent invention is explained. At the start of the operation of thecircuit arrangement shown in FIG. 3, a charging voltage across thecapacitor C3 is determined by a voltage division ratio of the resistorsR3 and R4; when R3=R4, V_(GC) =1/2 Vs. Consideration will be made of asituation that a gate drive signal Vin in the form of positive voltagepulse as illustrated in FIG. 4 is applied between the gate and sourceE-C of the MOSFET Q2. This signal Vin is a voltage between the nodes Eand C and accordingly may be represented by V_(EC). This representationwill correspondingly be applied to the voltages between other relatednodes hereinafter. Assume also that the gate drive signal Vin is largerthan the threshold voltage (about 3 V) of the MOSFET Q2, for example, 10V. The application of the gate drive signal Vin renders the MOSFET Q2 toa low impedance condition, so that the drain potential instantaneouslyfalls to the source potential or a potential value close to the commonpotential. With the fall of the drain potential, the voltage V_(BC)between the drain and source B-C of the MOSFET Q2 suddenly falls, asillustrated in FIG. 4. As a result, a positive voltage like the voltageV_(DB) illustrated in FIG. 4 appears between the gate and source D-B ofthe MOSFET Q1, so that the MOSFET Q1 is switched to ON state.

Consideration will be further made in more detail with respect to theoperation of the circuit arrangement during this process. The voltageV_(DB) has at the initial part of its pulse a value obtained bysubtracting a voltage across the resistor RG and the ON voltage acrossthe MOSFET Q2 from a voltage across the capacitor C3. Concerning thecurrent flowing at the time that the MOSFET Q2 is conductive, thecurrent flows through a route G→RG→ZD1→drain-source path of Q2 C, whenthe potential at the node G is higher than the voltage sum of a Zenervoltage V_(z1) of the Zener diode ZD1 and the ON voltage of the MOSFETQ2. The current flows through a route G→RG→gate-source ofQ1→drain-source of Q2→C when the potential at the node G is lower thanthe voltage sum of the Zener voltage V_(z1) of the Zener diode ZD1 andthe ON voltage of the MOSFET Q2. In this way, when the MOSFETs Q1 and Q2are both turned on, a load current I_(L) flows through the load resistorRL to the MOSFETs Q1 and Q2. The load current I_(L) is determined by theON resistances of the MOSFETs Q1 and Q2 and the load resistor RL. The ONresistance of the MOSFET Q2 is determined by the gate drive signal Vinand a forward transfer conductance of the MOSFET Q2 and the ONresistance of the MOSFET Q1 is also determined by the voltage V_(DB) anda forward transfer conductance of the MOSFET Q1. Among those resistancesexisting in the main circuit RL→Q1→Q2, the load resistor RL has a fixedvalue and the ON resistance of the MOSFET Q2 is controlled by a crestvalue of a positive pulse voltage Vin (V_(EC)) applied between the gateand source of the MOSFET Q2 from exterior. Accordingly, in order toprovide the load current I_(L) with a sufficient magnitude, it isnecessary to apply a proper positive voltage between the gate and sourceD-B of the MOSFET Q1 by the gate bias circuit R3, R4, C3 and C4.

When the MOSFETs Q1 and Q2 are both turned on, the potential at the nodeA is Vs-I_(L) RL. At this time, if C3=C4 and R3=R4, then the potentialat the node G drops by I_(L) ×RL/2 from the initial value. As a result,there is a possibility that the MOSFET Q1 fails to maintain its ONstate. In addition, if the MOSFETs Q1 and Q2 are turned on, the chargestored in the capacitor C3 discharges through the path of G→RG→ theinput capacitance of the MOSFET Q1. An amount of charge dischargedthrough this path is determined by the input capacitance of the MOSFETQ1, if the discharge by the leak currents flowing through the gate andsource D-B of the MOSFET Q1 and the Zener diode ZD1 is negligible. Ingeneral, the input capacitance of the MOSFET greatly changes during itsON period. As seen from the waveforms of the drain current I_(D) and thedrain-source voltage V_(DS) at the time of turning on, the inputcapacitance Cin of the MOSFET is so selected to have the maximum valuein a phase II of three phases I, II and III of the turn-on period, andits value Cin (II) is given by the following equation:

    Cin(II)=Ciss-AvCrss

where

Av=ΔVds/ΔVgs, where ΔVds and ΔVgs are increments of drain-source andgate-sources voltages respectively.

Crss=Cgd

Ciss: Static input capacitance described in a catalogue

Cgd: Capacitance between gate and drain described in the catalogue

In an actual operation, the value Cin(II) may have a value ten timeslarger than the Ciss due to a Miller effect for the capacitance Cgdbetween the gate and drain. Accordingly, if the capacitance of thecapacitor C3 is small and C3≃C4, the charge reallocation by thedischarge through the capacitor C4 and the dynamic input capacitance ofthe MOSFET Q1 at the initial state of the turn-on does not biassufficiently positively the voltage V_(DB) between the gate and thesource D-B of the MOSFET Q1. Therefore, the MOSFET Q1 was not turnedsufficiently on.

As will be understood from the above consideration, in order to apply asufficient positive bias voltage between the gate and source of theMOSFET Q1 over a period of the turn-on time, the present inventionselects a value of the capacitor C3 to be 5 to 10 times larger than thatof the capacitor C4 thereby to decrease the voltage drop rate across thecapacitor C3 due to the discharge through the capacitor C4 over aturn-on transient period, and further to charge the dynamic inputcapacitor of the MOSFET Q1 up to a proper positive voltage. Moreparticularly, the capacitance of the capacitor C3 is determined to be 5to 10 times larger than the static input capacitance of the MOSFET Q1 inaccordance with the pulse width and the capacitance of the capacitor C4is selected to be approximately 2/3 to 1/several of the capacitance ofthe capacitor C3, so that the MOSFET Q1 is turned sufficiently on.

Let us consider now a turn-off period of the MOSFET Q1. The capacitanceof the capacitor C3 is larger than that of the capacitor C4 and theresistance of the resistor R4 is large, and thus a voltage rise rate ofthe capacitor C3 is slow, so that the potential at the node B approachesfaster to a value equal to 1/2 of the power source voltage than thepotential at the node G. As a result, the charge current to thecapacitor C3 flows from the node B through the Zener diode ZD1 in theconductive direction (where the voltage drops by about 0.6 to 0.7 V) andthe resistor RG. As a result, the gate and source path of the MOSFET Q1is inversely biased by about 0.6 to 0.7 V, thereby improving theturn-off speed.

Further, the resistor RG is for controlling the respective peak valuesof the discharge current to a path C3→RG→D→B→Q2→C during the turn-onperiod and the charging current to a path B→ZD1→RG→C3 during theturn-off period.

Specific values of the respective components in the circuit arrangementshown in FIG. 3 are illustrated below.

Power source voltage Vs: 400 V

Load resistor RL: 30Ω

MOSFETs Q1 and Q2: HEX2

Resistors R3=R4: 100 KΩ

Resistor RG: 200Ω

Static input capacitance (HEX2) Ciss: 450 pF

Capacitor C3=10×Ciss: 0.005 μF

Capacitor C4=(1/2.5) C3: 0.002 μF

Zener voltages V_(Z1) and V_(Z2) : 19 V

Resistor Rs: 15Ω

Capacitor C₅ : 0.0022 μF

Resistor R_(E) : 20 KΩ

In the circuit arrangement with the above-mentioned circuit constants,the maximum values of the voltages V_(AB) and V_(BC) were 200 V and themaximum value of the voltage V_(DB) was 19 V and the maximum value ofthe current I_(L) was 6 A, when the gate drive pulse Vin was 10 V.

While the present invention has been described with reference to theembodiment of the circuit arrangement which employs two MOSFETsconnected in series, it is clear that the invention is applicable to anFET transistor circuit arrangement having a desired numbers of (two ormore) MOSFETs. An embodiment of a MOSFET transistor circuit arrangementaccording to the invention having a plurality of n MOSFETs connected inseries is shown in FIG. 6. In FIG. 6, like reference symbols are used todesignate corresponding portions in FIG. 3. In FIG. 6, Q3 is a MOSFETcorresponding to the MOSFET Q1 and ZD3 is a protective Zener diode likethe Zener diode ZD1. A gate bias circuit for the MOSFET Q3 is comprisedof capacitors C5 and C6 and resistors R5 and R6. The capacitors C5 andC6 correspond respectively to the capacitors C3 and C4; the resistors R5and R6 correspond respectively to the resistors R3 and R4. The conditionfor selecting the capacitances of the capacitors C5 and C6 correspondsto that of the capacitors C3 and C4 and therefore no detaileddescription will be given here.

FIG. 7 shows another embodiment of a circuit arrangement according tothe invention in which three or more MOSFETs are connected in series. InFIG. 7, like portions are designated by like reference symbols used inFIG. 6. In this embodiment, parallel connection circuits respectivelyhaving pairs of a resistor R11 and a capacitor C11, a resistor R12 and acapacitor C12, and a resistor R13 and a capacitor C13, are connected inseries. The series connection circuit including those parallelconnection circuits has one end X connected to a common potential pointand the other end Y connected to the drain of the MOSFET Q3 on the sideof the power source. The nodes Z1 and Z2 between the adjacent parallelconnection circuits are connected to the gates of the correspondingMOSFETs Q1 and Q3, respectively. The capacitances of those capacitorsC11, C12 and C13 are so selected that the capacitance of the capacitorC11 on the side of the common potential is the greatest and thesubsequent capacitors are stepwisely reduced in the sequence of thecapacitor connecting order; i.e., C11 C12 C13. The respectivecapacitances of the capacitors C11, C12 and C13 are each about 5 to 10times larger than the input capacitance of the respective MOSFETs. Theresistances of the resistors R11, R12 and R13 may be selected to beequal to one another. While the embodiment shown in FIG. 7 uses threeMOSFETs connected in series, the number of the MOSFETs may be increased,if necessary, as a matter of course.

While in the above-mentioned embodiments, the present invention has beenexplained in the case of n-channel MOSFETs, the present invention can beapplied to a series connection circuit arrangement having p-channelMOSFETs, junction FETs (J FET), MONOS FETs, or other insulated gatefield effect transistors.

INDUSTRIAL APPLICABILITY

As described above, the field effect transistor circuit arrangementaccording to the invention uses a gate bias circuit which does notrequire an additional DC power source in order to control the ON and OFFof the respective gate of the field effect transistors connected inseries. Therefore, unlike the gate drive by a pulse transformer, thecircuit arrangement is free from the restriction of the operatingfrequency and operable without an additional power source. Consequently,the invention greatly contributes the reduction of costs of the circuitarrangement of this type.

I claim:
 1. A field effect transistor circuit arrangement including aplurality of field effect transistors having first and second electrodesand a control electrode, and a load (RL), which are connected in aseries arrangement between a power source voltage point (Vs) and acommon potential point (C), comprising:means for applying a controlpulse (Vin) to the control electrode of one of said field effecttransistors which is connected in said series arrangement on the side ofthe common potential point; at least one first parallel connectioncircuit having a first resistor and a first capacitor, each firstparallel connection circuit being coupled between the control electrodeof a respective one of the remaining field effect transistors and thecommon potential point; at least one second parallel connection circuithaving a second resistor and a second capacitor, each second parallelconnection circuit being coupled between a respective first parallelconnection circuit and the first electrode of one of said remainingfield effect transistors which is connected in said series arrangementon the side of the power source voltage point, a capacitance of saidfirst capacitor in said first parallel connection circuit being largerthan that of said second capacitor in said second parallel connectioncircuit; a Zener diode connected between the second electrode and thecontrol electrode of each of said field effect transistors forpreventing a voltage applied therebetween from exceeding a predeterminedbreakdown voltage between the control electrode and second electrode ofeach of said field effect transistors; and said remaining field effecttransistors being changed to a conductive state at the time that saidcontrol pulse is applied to said one field effect transistor.
 2. A fieldeffect transistor circuit arrangement as claimed in claim 1, in which athird resistor (R_(G)) for current restriction is connected between saidcontrol electrode of each of said remaining field effect transistors anda connection point between said first and second parallel connectioncircuits.
 3. A field effect transistor circuit arrangement as claimed inclaim 2, wherein fourth resistors are respectively inserted between saidfirst electrodes and said second electrodes of said field effecttransistors, for correcting an unbalance of voltages shared by saidfield effect transistors due to variations of the characteristics ofleak current between said first and second electrodes among said fieldeffect transistors.
 4. A field effect transistor circuit arrangement asclaimed in claim 3, in which a series connection circuit having a fifthresistor and a third capacitor is connected between said first electrodeand said second electrode of each of said field effect transistors, forcorrecting an unbalance of voltages shared by said field effecttransistors due to variations of switching characteristics among saidfield effect transistors.
 5. A field effect transistor circuitarrangement as claimed in claim 1, in which the capacitance of saidfirst capacitor is approximately 5 to 10 times larger than a staticinput capacitance of a respective field effect transistor.
 6. A fieldeffect transistor circuit arrangement as claimed in claim 1, in which acapacitance of said second capacitor is selected to be about 2/3 to1/several of the capacitance of said first capacitor.
 7. A field effecttransistor circuit arrangement including a plurality of field effecttransistors having first and second electrodes and a control electrode,and a load which are connected in a series arrangement between a powersource voltage point (Vs) and a common potential point (C),comprising:means for applying a control pulse (Vin) to the controlelectrode of one of said field effect transistors which is connected insaid series arrangement on the side of the common potential point; afirst parallel connection circuit having a resistor and a capacitorcoupled between the common potential point and the control electrode ofone of the remaining field effect transistors which is connected in saidseries arrangement adjacent to the field effect transistor which isconnected on the side of the common potential point; a plurality ofadditional parallel connection circuits each having a resistor and acapacitor connected in parallel, said plurality of additional parallelconnection circuits being connected in series between said firstparallel connection circuit and the first electrode of one of said fieldeffect transistors which is connected in said series arrangement on theside of said power source voltage, the capacitance of the capacitors insaid first and plurality of additional parallel connection circuitsbeing so selected that the capacitance of the capacitor of said firstparallel connection circuit is the greatest and the subsequentcapacitors in the series connection of said additional parallelconnection circuits are stepwisely reduced in capacitance in thesequence of the connecting order of said additional parallel connectioncircuits and that the respective capacitances of the capacitors of saidfirst and additional parallel connection circuits are each about 5 to 10times larger than the input capacitance of a respective one of saidremaining field effect transistors; respective connection points of saidseries connected first and plurality of additional circuits beingelectrically coupled to respective control electrodes of said remainingfield effect transistors; a Zener diode connected between the secondelectrode and the control electrode of each of said field effecttransistors for preventing a voltage applied therebetween from exceedinga predetermined breakdown voltage between the control electrode andsecond electrode of each of said field effect transistors; and saidremaining field effect transistors being changed to a conductive stateat the time that said control pulse is applied to said one field effecttransistor connected on the side of the common potential point.